Flash memory devices typically are electrically erasable and/or programmable and are often used for data storage in relatively large units. Flash memory is widely used, for example, for storing a basic input/output system (BIOS) in place of a hard disk, for storing a communication protocol in a mobile phone, as an image memory in a digital camera, and other storage application.
NOR-type flash memory devices typically have a significantly greater programming and read speed in comparison to other types of nonvolatile memory devices. A typical NOR-type flash memory device includes memory cells positioned at respective intersections of word lines and bit lines. Each memory cell typically includes a control gate and a floating gate positioned between a source region and a drain region. The control gates typically are coupled to word lines, the drain regions are typically coupled in common to a bit line, and the source region is typically grounded. The floating gate typically is disposed between a channel region and the control gate.
FIG. 1 is a block diagram schematically illustrating a conventional NOR-type flash memory device. Memory blocks BLK, 10, 12, 14 and 16 and a sense amplifier S/A, 20 are illustrated. For example, the memory block 10 may have 512K memory cells, the number of word lines WL may be 1024 and the number of bit lines BL may be 512. The word lines are connected to row decoders X-DEC, 30 and 31, and the bit lines are selectively connected to the sense amplifier 20 through a column pass circuit Y-PASS 40 in response to a column decoded signal output from a column decoder. A row decoder may select one word line and a column decoder may select one bit line. The sense amplifier 20 senses whether a selected cell is an “off” cell or “on” cell, amplifying a bit line voltage according to a state of a memory cell connected to a selected word line and selected bit line.
FIG. 2 is a circuit diagram illustrating a memory cell of a memory block of the memory device of FIG. 1. A memory cell includes a cell transistor CTR1. The cell transistor CTR1 includes a control gate and a floating gate. The control gate is connected to a word line WL. A drain of the cell transistor CTR1 is connected to a bit line BL and a source is connected to a ground terminal through a source line SL.
FIG. 3 is a circuit diagram illustrating a conventional read operation of a NOR-type flash memory device as illustrated in FIGS. 1 and 2. When a cell transistor CTR10 is selected, a word line S_WL and a bit line S_BL connected to the cell transistor CTR10 are selected. Other word lines US_WL connected to other cell transistors CTR12-15 in other rows of cell transistors are unselected, and a bit line US-BL connected to cell transistors CTR11, CTR13, CTR15 is unselected. The selected bit line S_BL is selected by coupling it to the sense amplifier S/A using a column pass transistor SW1 in response to a column selection signal yi. The unselected bit line US-BL is disconnected from the sense amplifier S/A by turning off a column pass transistor SW2 in response to another column selection signal yj.
In a read operation, when a voltage, e.g., 5V, is applied to the selected word line S_WL, and 0V is applied to the unselected word lines US_WL, and the selected cell transistor CTR10 connected to the selected word line S_WL and the selected bit line S_BL is an “off” cell, cell current Icell may be approximately 0, which causes the voltage of the selected word line S_BL, which is precharged, to remain at a logic “high” value. If the selected cell transistor CTR10 is an “on” cell, cell current Icell has a larger value which, after passage of a certain amount of time, causes the voltage of the selected bit line S_BL to approach a logic “low.” To read a state of the selected cell, the sense amplifier S/A is turned on at an appropriate time point in response to the column selection signal yi and performs a sense and amplification operation.
FIG. 4 is a circuit diagram illustrating a conventional program operation of a NOR-type flash memory device. To program a selected cell transistor CTR20 connected to a word line S_WL and a bit line S_BL to an “off” condition, a program voltage, for example, 10V, is applied to the selected word line S_WL. A bias voltage, for example, 5V, is applied to the selected bit line S_BL, while unselected word lines US_WL connected to unselected cell transistors CTR21, CTR22, a source line SL, and unselected bit lines (not shown) are grounded. This bias condition supports a program scheme using a channel hot electron (CHE) injection, in which a threshold voltage of cell transistor is increased by injecting hot electrons into a floating gate of the selected cell CTR20. The programmed flash memory cell CTR20 prevents current flow from a drain region thereof to a source region thereof.
FIG. 5 is a circuit diagram illustrating a conventional erase operation for a NOR-type flash memory device. To erase a memory cell transistor CTR51, a bit line BL and a source line SL are floated. A negative voltage, for example, −8V, is applied to a word line WL. A bulk voltage Vbulk, for example, 8V, is applied to a substrate of the cell transistor CTR51. The word line voltage and substrate (bulk) voltage are examples, and other voltage levels may be used. Electrons in the floating gate move via Fowler-Nordheim (FN) tunneling through a tunnel oxide layer to the semiconductor substrate. The tunneling may be induced by forming a relatively high electric field between the floating gate of the memory cell CTR51 and the semiconductor substrate.
FIG. 6 is a circuit diagram of a conventional decoder used to select word lines in the memory device shown in FIG. 1. The decoder selects one of a plurality of local word lines WL<0>-WL<7> (connected to respective pluralities of cells) in response to a combination of signals applied to a read global word line GWL_RD or a write global word line GWL_WT and corresponding one of a plurality of a partial word lines PWL<0>-PWL<7>. For example, to select a local word line WL<0> for a read operation, a read global word line GWL_RD is driven to a “high” level to turn on an NMOS transistor NM61. A current driving capability of PMOS transistors PM61 and PM62 is lower than that of the NMOS transistor NM61, so a node N60 is driven to the voltage of a line nSS_RD, which has a voltage of approximate 0V in a read operation.
When a partial word line PWL<0> is selected, a local word line WL<0> takes on a voltage supplied to the partial word line PWL<0>. For example, the partial word line PWL<0> may driven to approximately 5V, while other partial word lines PWL<1>-PWL<7> are maintained at approximately 0V. Complementary partial word lines nPWL<0>˜nPWL<7> corresponding to the partial word lines PWL<0>-PWL<7> have logic levels opposite to the partial word lines PWL<0>-PWL<7>. For example, when the partial word line PWL<0> is at approximately 5V, a complementary partial word line nPWL<0> has a low level, e.g., approximately 0V, which turns off NMOS transistor NM64. The partial word lines PWL<1>-PWL<7> are at approximately 0V and the complementary partial word lines nPWL<1>-nPWL<7> have a high level, e.g., VCC level, which turns on corresponding NMOS transistors NM65.
An external voltage Vex is provided to unselected local word lines. The external voltage Vex may be a ground voltage VSS. For example, when the read global word line GWL_RD or the write global word line GWL_WT is unselected, the node N60 has a Vpx level, and NMOS transistors NM63, NM65 of the local word line drivers 60-67 are turned on. Approximately 0V is applied to partial word lines PWL<0>-PWL<7>, and complementary partial word lines nPWL<0>-nPWL<7> have a complementary voltage, e.g., VCC, which turns on NMOS transistors NM64 and NM66. Thus, local word lines WL<0>-WL<7> take on the external voltage Vex, which may be a ground voltage of around 0V. The NMOS transistors NM64 and NM66 and complementary partial word lines nPWL<0>˜nPWL<7>, which can prevent floating of unselected local word line in the decoder, may complicate the structure of the decoder and unduly increase its size.